1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and particularly relates to a flash memory capable of reducing a memory cell area.
2. Description of the Related Art
A nonvolatile semiconductor memory device represented by a flash EEPROM (Electrically Batch Erasable, Programmable ROM to be referred to as xe2x80x9cflash memoryxe2x80x9d hereinafter) is capable of storing data in a nonvolatile manner and no power supply is required to hold the data.
FIG. 17 is a partly enlarged plan view of the memory cell array of a conventional flash memory.
Referring to FIG. 17, a plurality of source lines 1 and a plurality of drain lines 2 are alternately arranged. A plurality of control gate lines 4 are arranged to be orthogonal to plural source lines 1 and drain lines 2. Each of a plurality of floating gates 3 is arranged between source line 1 and drain line 2 right under control gate line 4. A memory cell MC is arranged to correspond to the intersections between control gate lines 4 and source lines 1 and drain lines 2.
Accordingly, if a minimum processed dimension is assumed as F, the memory cell area of memory cell MC is 4Fxc3x972F=8F2.
The main targets of memories are moved from personal computers to digital home appliances or communication equipment. Since the function of a mobile terminal such as a cellular phone or a PDA (Personal Digital Assist) improved, the mobile terminal requires a memory having a mass storage and a small area.
As such a memory having a mass storage and a small area, a flash memory which is a nonvolatile semiconductor memory device has been utilized. However, it is considered that the weight reduction and improvement in function of the mobile terminal continue. As a result, it is necessary to make the memory area of a flash memory smaller.
It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of reducing a memory area.
A nonvolatile semiconductor memory device according to the present invention includes a plurality of word lines, a plurality of bit lines, a plurality of nonvolatile memory cells, a plurality of latch circuits and a bit line select circuit. The plurality of word lines are arranged in rows. The plurality of bit lines are arranged in columns. The plurality of nonvolatile memory cells are arranged in the rows and the columns. The plurality of latch circuits are arranged to be electrically connected to the plurality of bit lines, and latch a plurality of pieces of data inputted externally. The bit line select circuit supplies a predetermined potential to the plurality of bit lines, and maintains potentials of the plurality of bit lines each supplied with the predetermined potential. The plurality of nonvolatile memory cells arranged in each of the rows are connected in series, and gates thereof are connected to the word line arranged in the row.
It is preferable that the bit line select circuit includes a plurality of bit line control circuits, a connection circuit and a predetermined potential generation circuit. The plurality of bit line control circuits are arranged to correspond to the plurality of bit lines, and control the potential supplied to the corresponding bit lines in response to the data latched by corresponding latch circuits. The connection circuit sequentially connects the plurality of latch circuits to the plurality of bit line control circuits in response to a clock signal. The predetermined potential generation circuit generates the potential supplied to the plurality of bit lines.
It is preferable that the plurality of nonvolatile memory cells includes: a plurality of normal nonvolatile memory cells; and a spare nonvolatile memory cell replacing a defective normal nonvolatile memory cell among the plurality of normal nonvolatile memory cells, that the plurality of bit lines includes: a plurality of normal bit lines; and a spare bit line connected to the spare nonvolatile memory cell, that the plurality of latch circuits include: a plurality of normal latch circuits arranged to correspond to the plurality of normal bit lines, respectively; and a spare latch circuit arranged to correspond to the spare bit line, that the nonvolatile semiconductor memory device further includes: an address counter, a redundancy circuit, a write circuit, and a data latch circuit. The address counter outputs an address signal. The redundancy processing circuit determines whether the address signal is consistent with a defective address signal indicating the defective normal nonvolatile memory cell. The write circuit sequentially writes the plurality of pieces of data to the plurality of latch circuits, respectively, in response to the address signal in a write operation. The data latch circuit latches the data inputted and outputted into and from the spare nonvolatile memory cell. The write circuit transmits the data to the data latch circuit when the address signal is consistent with the defective address signal as a result of determination of the redundancy processing circuit, and writes the data latched by the data latch circuit to the spare latch circuit when the address signal designates the spare latch circuit.
A semiconductor memory device according to the present invention includes: a memory cell array and a select circuit. The memory cell array includes a plurality of word lines arranged in rows, respectively, a plurality of bit lines arranged in columns, respectively, and a plurality of memory cells arranged in the rows and the columns, respectively. The select circuit selects one of the plurality of memory cells. In the memory cell array, a plurality of memory cells arranged in each of the rows are connected in series, gates of the plurality of memory cells are connected to the word line arranged in the row, each of the plurality of bit lines is connected to a plurality of memory cells arranged in the two adjacent columns, and the select circuit first selects the memory cell located at an end of the memory cell array.
A semiconductor memory device according to the present invention includes a plurality of normal memory cells, a spare memory cell, and a redundancy circuit. The redundancy circuit determines in which of the plurality of normal memory cells and the spare memory cell, each of a plurality of pieces of data inputted externally is stored, controls a write operation, reads the data stored in the spare memory cell, and then determines which of the data stored in the plurality of normal memory cells and the data stored in the spare memory cell is outputted.
The nonvolatile semiconductor memory device in accordance with the present invention enables reduction in chip area, as the adjacent nonvolatile memory cells in the memory share a bit line. Further, even in the memory cell array structure in which the adjacent nonvolatile memory cells in the memory share a bit line, data can be successively written to the nonvolatile memory cells.